This invention relates generally to CMOS logic circuits, and more particularly, to a combined circuit configuration for a CMOS logic inverter and multi input logic gate.
A typical combined CMOS circuit 10 implementing an inverter and a two input NAND gate having a common input is shown in FIG. 1. P-channel transistor M1 and N-channel transistor M2 form an inverter. The coupled gates of transistors M1 and M2 form the input at circuit node 12, which receives logic signal A. The coupled drains of transistors M1 and M2 form the output at circuit node 22, which provides an inverted logic signal A*. The source of transistor M1 is coupled to a first source of supply voltage, designated VDD, at circuit node 15. The source of transistor M2 is coupled to a second source of supply voltage, designated VSS, at circuit node 17. CMOS logic levels typically require a five volt VDD power supply voltage and a zero volt VSS power supply voltage. These voltage levels can change depending upon the application and feature size of the CMOS transistors used.
Transistors M3 through M6 form a NAND gate. The coupled gates of P-channel transistor M4 and N-channel transistor M6 form the first input of the NAND gate, and are coupled to circuit node 12, sharing the common logic signal A. The source of transistor M4 is coupled to power supply VDD and the drain of transistor M4 is coupled to the output of the NAND gate. The source of transistor M6 is coupled to power supply VSS and the drain of transistor M6 is coupled to the source of transistor M5. The coupled gates of P channel transistor M3 and N-channel transistor M5 form the second input of the NAND gate at circuit node 14. The second input receives a second logic signal B. The coupled drains of transistors M3 and M5 are coupled to the output of the NAND gate at circuit node 18. Six transistors are required to implement the combined inverter and NAND gate of circuit 10.
In operation, the NAND gate of FIG. 1 responds to four separate logic states to provide the logical NAND function. The logical input states, status of each transistor, and output logical level are shown below in Table One. A transistor is labeled off if the gate-to-source voltage is zero, or is prevented from conducting current due to a series transistor that is off.
TABLE 1 ______________________________________ A B M3 M4 M5 M6 Output ______________________________________ 0 0 on on off off 1 0 1 off on off off 1 1 0 on off off off 1 1 1 off off on on 0 ______________________________________
A typical combined CMOS circuit 30 implementing an inverter and a two input NOR gate having a common input is shown in FIG. 3. The inverter is identical to the inverter of circuit 10. The inverter and the NOR gate have a common input for receiving logic signal A on circuit node 12.
Transistors M3 through M6 form the NOR gate. The coupled gates of P-channel transistor M3 and N-channel transistor M6 form the first input of the NOR gate at circuit node 12, which receives the first logic signal A. The coupled gates of P-channel transistor M4 and N-channel transistor M5 form the second input of the NOR gate at circuit node 14, which receives the second logic signal B. The coupled drains of transistors M4 and M6 are coupled to the output of the NOR gate at circuit node 18. The source of transistor M4 is coupled to the drain of transistor M3. The source of transistor M3 is coupled to supply voltage VDD and the source of transistors M5 and M6 are coupled to supply voltage VSS. The drain of transistor M6 is coupled to the output of the NOR gate. Six transistors are also required to implement the combined inverter and NOR gate of circuit 30.
In operation, the NOR gate of FIG. 3 also responds to four separate logic states to provide the logical NOR function. The logical input states, status of each transistor, and output logical level are shown below in Table Two. A transistor is labeled off if the gate-to-source voltage is zero, or is prevented from conducting current due to a series transistor that is off.
TABLE 2 ______________________________________ A B M3 M4 M5 M6 Output ______________________________________ 0 0 on on off off 1 0 1 off off on off 0 1 0 off off. off on 0 1 1 off off on on 0 ______________________________________
A typical combined CMOS circuit 50 implementing an inverter and a three input NAND gate having a common input is shown in FIG. 5. The inverter is identical to the inverter of circuit 10. The inverter and the NOR gate have a common input for receiving logic signal A on circuit node 12.
Transistors M3 through M8 form the NAND gate. The coupled gates of P channel transistor M5 and N-channel transistor M8 form the first input of the NAND gate at circuit node 12, which receives the first logic signal A. The coupled gates of P-channel transistor M3 and N-channel transistor M6 form the second input of the NAND gate at circuit node 14, which receives the second logic signal B. The coupled gates of P-channel transistor M4 and N-channel transistor M7 form the third input of the NAND gate at circuit node 16, which receives the third logic signal C. The coupled drains of transistors M3 through M6 are coupled to the output of the NAND gate at circuit node 18. The drain of transistor M8 is coupled to the source of transistor M7, and the drain of transistor M7 is coupled to the source of transistor M6. The source of transistors M3 through M5 are coupled to supply voltage VDD and the source of transistor M8 is coupled to supply voltage VSS. A total of eight transistors is required to implement the combined inverter and three input NAND gate of circuit 50.
In operation, the NAND gate of FIG. 3 also responds to eight separate logic states to provide the logical NOR function. The logical input states, status of each transistor, and output logical level are shown below in Table Three. A transistor is labeled off if the gate-to source voltage is zero, or is prevented from conducting current due to a series transistor that is off.
TABLE 3 ______________________________________ A B C M3 M4 M5 M6 M7 M8 Output ______________________________________ 0 0 0 on on on off off off 1 0 0 1 on off on off off off 1 0 1 0 off on on off off off 1 0 1 1 off off on off off off 1 1 0 0 on on off off off off 1 1 0 1 on off off off off off 1 1 1 0 off on off off off off 1 1 1 1 off off off on on on 0 ______________________________________
What is desired is a combined inverter and logic gate circuit that can provide the same logic function as the prior art circuits 10, 30, and 50, as well as other similar circuits, with one less transistor, in order that integrated circuit area is conserved.